The present invention relates to high performance digital tuners having high sample rate parallel cascaded-integrator-comb filters.
Digital filters are used in a variety of communication systems which typically transmit and receive amplitude and/or phase modulated signals across a communication channel. Of course, the class or type of filter utilized depends upon the requirements of the particular application. Some applications, including those having phase modulated communication protocols, require filters with a constant group delay over the frequency range of interest, i.e. filters with a linear phase characteristic. Finite impulse response (FDR) filters may be designated with a linear phase characteristic while also providing selectable frequency characteristics. These filters are typically implemented using an array of multipliers to multiply various coefficients by consecutive input samples to achieve an overall desired frequency response. However, for many applications, FIR filter implementations are more complex and require more power than a cascaded-integrator-comb (CIC) filter having similar characteristics.
As described in detail in E. B. Hogenauer, xe2x80x9cAn Economical Class of Digital Filters for Decimation and Interpolation,xe2x80x9d IEEE Transactions on Acoustics, Speech and Signal Processing, Volume ASSP-29, No. 2, April 1981, pp. 155-162, and hereby incorporated by reference, CIC filters provide the same frequency response as several cascaded FIR Filters operating at the input sample rate followed by a downsampler. The number of cascaded stages is selected based on predetermined design requirements for aliasing or imaging error. However, the CIC filters may be implemented with significantly simpler logic than analogous FIR digital filters because the CIC implementation requires no multipliers and uses only limited storage. The reduced number of logic gates required for implementation improves efficiency and requires significantly less power. However, serial implementations for CIC filters as described by Hogenauer have limited sampling rates.
A parallel processing implementation for integrator stages of a CIC filter is described in detail in U.S. Pat. No. 5,596,609, the disclosure of which is hereby incorporated by reference in its entirety. The parallel CIC (PCIC) structure replaces serial integrators with parallel versions which can process effective input sample rates that are P times higher than a standard integrator clock rate, where P represents the number of parallel data words. Input samples are demultiplexed such that consecutive samples are applied to sequential inputs of the parallel structure. Adder and accumulator blocks include output pipeline registers to provide maximum operational speed with appropriate register blocks to equalize pipeline delays for the various paths. The PCIC structure is easily cascadeable since it allows subsequent integrator stages access to intermediate samples generated by preceding integrator stages. The parallel integrator structure may be implemented directly or maybe reduced in complexity by removing redundant logic for use in decimator output sections or interpolator input sections. The parallel implementation of a CIC filter allows much higher sample rate filtering to be implemented with fewer standard CMOS logic devices because the PCIC filter processes an effective input sample rate which is P times the input clock frequency. While the maximum input clock frequency depends upon the particular hardware or software used to implement the filter, potential clock harmonic interference may limit the tunable bandwidth and/or performance of the filter.
The present invention provides a PCIC based tuner with an input clock rate enabling a wide tuning bandwidth to reduce or minimize clock harmonic interference.
The present invention also provides a method for selecting an input clock rate for a PCIC-based tuner which maximizes tuning bandwidth while minimizing clock harmonic interference.
In accordance with the present invention, there is provided a digital tuner designed to maximize tuning range for a particular intermediate frequency. The digital tuner includes an analog to digital converter operating at an input clock frequency to sample an analog input signal and produce a multi-bit digital word for each sample, a demultiplexer in communication with the analog to digital converter converts serial samples from the analog to digital converter to parallel samples for input to a plurality of mixers. A plurality of local oscillators interconnected to corresponding ones of the plurality of mixers, and a parallel cascaded integrator comb filter coupled to the plurality of mixers filters and decimates the parallel samples wherein the mixers, the local oscillators, and the filter operate at a frequency having adjacent harmonics substantially centered about the intermediate frequency. In one embodiment, a tuner for use with a phase modulated signal includes a plurality of quadrature multipliers functioning as mixers and driven by coherent local oscillators each including a phase accumulator and cosine/sine look-up tables. Separate PCIC filters are provided for filtering and decimating the resulting phase (I) and quadrature (Q) signals for direct application to a demodulator, or to a decimating CIC or FIR filter for subsequent sample rate reduction. Preferably, the local oscillators, quadrature multipliers and PCIC filters are incorporated into a single programmable logic device, such as a field programmable gate array (FPGA), an embedded programmable logic device (EPLD), or application-specific integrated circuit (ASIC).
A method for determining an operating frequency for a digital tuner having an associated intermediate frequency to reduce clock harmonic interference includes determining a maximum frequency based on operating parameters of tuner elements, selecting a harmonic of the operating frequency based on the intermediate frequency and the maximum frequency, and selecting the operating frequency based on the intermediate frequency and the selected harmonic to enhance tuning bandwidth and reduce clock harmonic interference.
The present invention provides a number of advantages for PCIC filter applications including digital tuners. For example, selection of a clock frequency according to the present invention is based on harmonics around the intermediate frequency to enhance the tuning range without potential clock harmonic interference. Implementation of a local oscillator including a phase accumulator and sine/cosine look-up tables, in addition to mixer multipliers and one or more PCIC filters reduces the number of logic devices needed to implement a digital tuner. Tuners constructed according to the present invention are particularly suited for use as telemetry receivers requiring a wide tuning bandwidth, low spurious levels, and constant group delay characteristics. Furthermore, the high sampling rate afforded by the present invention eases design requirements for anti-aliasing filters while providing greatly improved group delay characteristics compared to an under sampled approach. Direct sampling also eliminates the oscillators and mixers required for analog tuning techniques which can generate undesired spurious signals through harmonics, coupling, and mixing processes.